Urce reg

Macros
#define	C6DOFIMU15_DEN_DRDY   0x80
#define	C6DOFIMU15_D6D_IA   0x40
#define	C6DOFIMU15_Z_AXIS_HIGH   0x20
#define	C6DOFIMU15_Z_AXIS_LOW   0x10
#define	C6DOFIMU15_Y_AXIS_HIGH   0x08
#define	C6DOFIMU15_Y_AXIS_LOW   0x04
#define	C6DOFIMU15_X_AXIS_HIGH   0x02
#define	C6DOFIMU15_X_AXIS_LOW   0x01

Detailed Description

Macro Definition Documentation

C6DOFIMU15_D6D_IA

#define C6DOFIMU15_D6D_IA   0x40

C6DOFIMU15_DEN_DRDY

#define C6DOFIMU15_DEN_DRDY   0x80

C6DOFIMU15_X_AXIS_HIGH

#define C6DOFIMU15_X_AXIS_HIGH   0x02

C6DOFIMU15_X_AXIS_LOW

#define C6DOFIMU15_X_AXIS_LOW   0x01

C6DOFIMU15_Y_AXIS_HIGH

#define C6DOFIMU15_Y_AXIS_HIGH   0x08

C6DOFIMU15_Y_AXIS_LOW

#define C6DOFIMU15_Y_AXIS_LOW   0x04

C6DOFIMU15_Z_AXIS_HIGH

#define C6DOFIMU15_Z_AXIS_HIGH   0x20

C6DOFIMU15_Z_AXIS_LOW

#define C6DOFIMU15_Z_AXIS_LOW   0x10